Lots of researches indicate that the inefficient generation of random numbersis a significant bottleneck for information communication applications.Therefore, Field Programmable Gate Array (FPGA) is developed to process ascalable fixed-point method for random streams generation. In our previousresearches, we have proposed a technique by applying some well-defined discretechaotic iterations that satisfy the reputed Devaney's definition of chaos,namely chaotic iterations (CI). We have formerly proven that the generator withCI can provide qualified chaotic random numbers. In this paper, this generatorbased on chaotic iterations is optimally redesigned for FPGA device. By doingso, the generation rate can be largely improved. Analyses show that thesehardware generators can also provide good statistical chaotic random bits andcan be cryptographically secure too. An application in the information hidingsecurity field is finally given as an illustrative example.
展开▼
